This invention relates to programmable logic devices, and more particularly to implementing configurable memory structures within such devices.
Common architectural features of programmable logic devices include a two-dimensional array of rows and columns of logic array blocks (LABs) and a programmable network of interconnection conductors for conveying signals between the LABs. The design of programmable logic devices may be enhanced by the addition of large memory blocks (e.g., random access memory (RAM) or read-only memory (ROM)) between the LABs (see, for example, Cliff et al. U.S. Pat. No. 5,689,195, and Jefferson et al. U.S. Pat. No. 6,215,326).
Such memory blocks are useful for storing large blocks of data and/or performing various logic functions that may be more efficiently performed in a single large memory block rather than in several LABs. However, there are some applications in which using these memory blocks may not be an efficient use of system resources. When applications use only a fraction of the available capacity of these memory blocks, for example, the chip area and the interconnect resources allocated to these memory blocks are not being used efficiently.
The present invention relates to an improved LAB that allows a user to programmably selectively implement a variety of different memory structures on a programmable logic device. The improved LAB is programmably configurable for operation in at least two modes: in a first mode, the LAB may be configured to perform logic functions; in a second mode, the LAB may be configured to implement various memory schemes (e.g., shift-registers, first-in-first-out (FIFO) memory, RAM/ROM, etc.).
The improved LAB that may be constructed in accordance with the principles of the present invention possesses several advantageous features over conventional LAB designs. For example, the improved LAB will allow a user to efficiently build modular memory structures in a programmable logic device by allowing the user to programmably configure, as necessary, specific LABs for implementing any of a variety of different memory schemes.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the invention.